Director of IC Packaging

A NauWork client is seeking a Director, IC Packaging Engineering to join their team. The position is on-site in greater San Jose, CA.

This venture-backed semiconductor innovator, headquartered in the greater San Jose area is redefining how data moves inside next-generation computing systems. Founded by seasoned leaders from the optical networking space and backed by top-tier VCs, the company focuses on ultra-low power, high-density optical interconnects for AI data centers, high-performance computing, and advanced semiconductor applications. Their microLED-based approach is solving interconnect bottlenecks that limit today’s AI and cloud infrastructures, enabling performance and efficiency levels that traditional electrical and laser-based solutions struggle to reach.

This Director, IC Packaging Engineering role sits at the center of that mission. The successful candidate will own the advanced packaging technology roadmap and execution for the company’s product portfolio, with particular emphasis on 3D integration and wafer-level bumping at scale. This leader will build and mentor a packaging organization, support technology introduction (NPI) from pathfinding through HVM transfer, and serve as the key interface to OSATs, foundries, and equipment partners. For an experienced packaging leader who wants to shape a category-defining technology stack rather than iterate on legacy platforms, this is an opportunity to have direct impact on architecture, manufacturing strategy, and organizational growth.

Responsibilities:

Lead the architecture, design, and development of advanced semiconductor packaging solutions, including 2.5D/3D IC, System-in-Package (SiP), Flip Chip, and Wafer-Level Packaging

Lead development, characterization, and optimization of TSV (Through-Silicon Via) reveal processes, including back grind, CMP, dielectric/barrier reveal etch, and thickness/uniformity control across wafer thinning stacks.

Partner with integration engineering to co-optimize TSV reveal with downstream hybrid bonding, micro-bump, or RDL processes

Own C4 bumping process flows — UBM deposition, solder bump plating or ball drop, reflow, and flux clean — for flip-chip and 3D-IC applications

Develop and maintain process control plans (SPC), DOEs, and yield improvement roadmaps for optical engine packaging and bumping modulesBuild, lead, and develop a high-performing team of packaging and process engineers, including hiring, mentoring, and performance management.

Serve as the primary point of contact for strategic OSAT and foundry partners and help drive their execution.

Develop, support, and mentor a packaging engineering team

Own excursion management and escalation processes, ensuring rigorous root-cause analysis using FA data, cross-sections, and metrology (e.g., CD-SEM, profilometry, XRF, AOI) for key defect modes.

Collaborate with design, reliability, quality, and test leadership to ensure package-level electrical, mechanical, and reliability requirements are met across the product line.

Support new product/technology introduction (NPI) from pathfinding through HVM transfer

Required Experience:

MS or PhD in Materials Science, Electrical Engineering, Chemical Engineering, Mechanical Engineering, or a closely related discipline.

10+ years of experience in semiconductor packaging or wafer fab process engineering, including at least 5 years leading and managing engineering teams.

Demonstrated success bringing advanced packaging technologies from plan/goals through development and execution to HVM hand-off.

Experience owning OSAT relationships and driving outcomes.

Direct technical expertise in TSV reveal processes (grinding, CMP, dielectric reveal, thickness metrology) and C4 bumping (UBM, electroplating or solder ball attach, reflow).

Strong understanding of 2.5D/3D packaging architectures, including interposers, chiplets, HBM integration, and hybrid bonding.

Strong command of semiconductor device physics, packaging materials, and thermal/mechanical analysis.

Proven experience building and governing SPC programs, DOE frameworks, and yield analysis at scale.

Familiarity with metrology and inspection tools relevant to bumping and TSV (CD-SEM, AFM, profilometers, X-ray, AOI/SEM defect review).

Working knowledge of cleanroom fab operations and contamination control.

Executive-level communication skills, comfortable presenting to leadership, customers, and partners, and aligning multi-site, cross-functional teams.

Nice to Have:

Experience with copper pillar bumping, micro-bump, and/or hybrid bonding processes.

Background in wafer thinning and temporary bonding/debonding for advanced-node packaging.

Experience defining reliability qualification strategies (e.g., thermal cycling, electromigration, HAST) for packaged devices.

Prior experience scaling an engineering organization through a major growth phase or high-volume manufacturing ramp.

Experience in optical interconnect, photonics, or micro-LED packaging.

To Learn More:

503-388-9585

833-NAU-WORK

careers.nauwork.com

Category: Engineering – Electrical (Semiconductor)

Position: Director, IC Packaging Engineering

Location: On-site – San Jose Area, CA

Job Type: Direct-Hire, Full-Time