Integrated Circuit (IC) Layout Designer

A NauWork client is seeking an IC Layout Designer to join their team. The position is onsite in Sunnyvale, California .

This privately held semiconductor technology company is developing next-generation, ultra-low-power interconnect solutions for high-bandwidth chip-to-chip communication. Its work has the potential to transform AI infrastructure, high-performance computing, cloud computing, autonomous systems, and other markets where efficient data movement is critical. Founded by accomplished optical networking technologists, the organization offers the opportunity to join a focused team addressing one of the semiconductor industry’s most important technical challenges.

The IC Layout Designer will create transistor-level physical layouts for analog, mixed-signal, and high-speed integrated circuits. Working closely with circuit designers, this individual will turn schematics into compact, manufacturable layouts that satisfy electrical, matching, parasitic, and reliability requirements. This is an opportunity to contribute across floorplanning, physical verification, extraction, integration, and tapeout while working with advanced semiconductor processes.

Responsibilities:

Design transistor-level IC layouts for analog, mixed-signal, and high-speed circuits.

Translate circuit schematics into clean, compact, and manufacturable physical layouts.

Lay out MOSFETs, resistors, capacitors, diodes, guard rings, ESD structures, and interconnect routing.

Apply common-centroid structures, symmetry, shielding, dummy devices, isolation, and other techniques that improve matching and reduce noise.

Run and debug DRC, LVS, ERC, antenna, density, and reliability checks.

Perform parasitic extraction and collaborate with circuit designers to minimize resistance, capacitance, coupling, and mismatch.

Support floorplanning, block-level integration, power routing, and top-level chip assembly.

Follow foundry design rules and process-specific layout requirements.

Optimize layouts for performance, power, area, yield, manufacturability, and long-term reliability.

Prepare layout databases for tapeout and assist with final verification and signoff.

Required Experience:

Associate degree, bachelor’s degree, or equivalent practical experience in electrical engineering, microelectronics, or a related discipline.

Hands-on experience with IC layout tools, preferably Cadence Virtuoso Layout Suite.

Strong understanding of CMOS device layout, semiconductor process layers, and analog layout principles.

Experience running and debugging DRC and LVS with Calibre, Pegasus, Assura, or comparable tools.

Ability to read and interpret circuit schematics.

Knowledge of parasitic effects, device matching, shielding, isolation, and signal integrity.

Strong attention to detail and the ability to consistently follow layout and foundry guidelines.

Effective communication and collaboration skills for working closely with circuit designers.

Experience laying out analog or mixed-signal blocks such as PLLs, ADCs, DACs, SerDes, bandgaps, regulators, amplifiers, oscillators, filters, or high-speed I/O is preferred.

Experience with advanced CMOS nodes, including 28 nm, 16 nm, 12 nm, 7 nm, or similar processes, is preferred.

Familiarity with FinFET layout constraints, top-level integration, ESD planning, chip finishing, electromigration, IR drop, latch-up prevention, and reliability rules is beneficial.

Layout automation experience using SKILL or Python is a plus.

To Learn More:

503-388-9585

833-NAU-WORK

careers.nauwork.com

Category: Engineering - Electrical (Semiconductor) Position: IC Layout Designer Location: Sunnyvale, California - Onsite Job Type: Direct-Hire, Full-Time