Principal SoC DFT Engineer

The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network Infrastructure Optical Network group

You will be working on DFT architecture and implementation across logic BIST, MBIST, BISR, Boundary Scan, and JTAG. This is a highly execution-driven role requiring end-to-end ownership of DFT insertion, verification, DRC closure, and test coverage closure from RTL/netlist through post-silicon debug. As a senior member of the DFT team, you will work closely with the architecture, IP design, Physical Design and product engineers to achieve first pass silicon success.

Perform hands-on DFT implementation and verification, including:

Logic BIST and scan compression

MBIST and BISR

Boundary Scan (IEEE 1149.x) insertion

JTAG insertion and connectivity

High-speed analog/mixed signal IP integration

Execute DFT verification, debug, and DFT DRC closure

Identify, debug, and resolve DFT rule violations at both block and top levels

Run, analyze, and debug DFT/RTL checks, working with design teams to close violations

Generate, simulate, and debug MBIST and logic ATPG patterns

Analyze test results and drive test coverage improvement and closure

Develop and validate DFT timing constraints for scan, BIST, and test modes

Create and maintain TCL scripts to automate DFT insertion, verification, and analysis flows

Support hierarchical DFT implementation and resolve integration issues

Collaborate with RTL and Physical Design teams to address DFT-related design issues

Support pre-silicon DFT signoff and assist with post-silicon pattern bring-up and debug

Assist with ATE pattern conversion and debug as needed

Experience with gate-level simulations and debugging with industry simulator tools

You Have:

Bachelor’s degree in computer science, Electrical Engineering or related fields and 8 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5 years of experience.

5+ years of hands-on DFT implementation experience

Strong proficiency with EDA tools , including: Logic BIST insertion and verification

MBIST / BISR insertion and verification

Boundary Scan (IEEE 1149.x)

JTAG and HS Analog/mixed signal IP IOBIST integration

ATPG pattern generation and coverage analysis

Proven ability to resolve DFT DRCs, connectivity issues, and testability problems

Strong TCL scripting skills for DFT automation and flow execution

Experience developing and validating scan and test-mode timing constraints

End-to-end DFT lifecycle experience, from RTL/netlist through silicon debug

Strong debugging skills, attention to detail, and sense of ownership

Excellent verbal and written communication skills