← Search all jobs

Principal Front-End Design Engineer

Synopsys

Sunnyvale, CA · Posted October 21, 2026

Just laid off? Start here: a plan for the first weeks

Want recruiters in Engineering to be able to find you?

Roles at this level, like this one at Synopsys, are often filled through recruiters.

See every open role at Synopsys

More in California job market · Technology & Software · Engineering jobs

More roles at Synopsys

Similar jobs

Where Sunnyvale, CA ranks

Where Sunnyvale, CA placed in our monthly rankings, month by month. Each month stays online at its own address.

How AI is used in this kind of work

Among web developers, AI is already used for a large share of the tasks. Measured exposure for web developers: 48% (high).

Share of this job’s tasks that AI is already used for at work, from real usage. It is not a forecast of job loss, and a low number means no use seen yet. Source: Anthropic Economic Index.

Check how this applies to your own job

Synopsys has filed one layoff notice in the last twelve months, covering 128 workers, most recently August 2026. These are public filings with state labor departments, and an open role can sit alongside them. See the filings

Skills this job asks for

Say which you have and which you want to build. We use it to match you to jobs like this one.

About the job

We Are

Synopsys is a leader in silicon-to-systems engineering solutions, helping customers accelerate innovation in AI-driven products through industry-leading EDA, IP, and design solutions.

You Are

As a Principal Front-End Design Engineer, you will lead methodology, subsystem architecture, and AI-enabled design innovation across IP and SoC development. You will build scalable design solutions, improve engineering productivity, and drive best practices across global teams.

What You'll Be Doing

Develop and deploy AI-driven solutions for verification, synthesis, constraints, and DFT workflows.

Architect reusable subsystem reference designs for Synopsys IP.

Debug and optimize front-end design methodologies and automation flows.

Drive adoption of best practices across design and verification teams.

Collaborate with EDA, IP, and customer-facing engineers to solve complex design challenges.

Mentor engineers through technical leadership and knowledge sharing.

What You'll Need

BS/MS in Electrical Engineering, Computer Engineering, or related field.

10+ years of ASIC, SoC, or IP design and verification experience.

Expertise in verification, synthesis, timing constraints, DFT, CDC/RDC, or lint methodologies.

Strong experience with Synopsys tools such as VCS, VC SpyGlass, Fusion Compiler, Design Compiler, and TestMAX.

Proficient in SystemVerilog, UVM, Tcl, Python, or similar languages.

Demonstrated technical leadership and influence across cross-functional engineering teams.

What Sets You Apart

Deep understanding of IP reuse, subsystem integration, and SoC development.

Passion for applying AI to improve design productivity and quality.

Strong problem-solving, communication, and mentoring skills.

Ability to translate complex technical challenges into scalable, practical solutions.

The Team You'll Be Part Of

You will be a member of the Digital Methodology Interop Engineering team, a team of engineers dedicated to advancing IP and subsystem design excellence at Synopsys. The team collaborates across global sites, driving innovation in methodology, tool integration, and best practices. You will help shape the future of SoC design with Synopsys IP.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.