Machine Learning Engineer, LLM Post-Training (Chip Design AI)

An AI startup creating agent software for semiconductor design and verification seeks an ML engineer to strengthen the language models underlying its product. The job spans model post-training, tuning and assessment, taking ideas from early research into dependable production use at chipmakers.

Responsibilities

Teach, adapt and refine language models aimed at semiconductor design and verification, using approaches like SFT and RL

Develop and maintain the data pipelines that feed training, covering gathering, scrubbing and artificially generated examples

Devise benchmarks and evaluation frameworks that gauge how accurate and dependable models and agents are on genuine engineering workflows

Run experiments, study their outcomes and iterate quickly toward better models

Partner with scientists on the research side, plus engineers who build systems and EDA veterans, to land new methods in production

Follow the latest papers and open-source projects, adopting the techniques that show promise

About you

Degree in CS, EE or a neighboring discipline (or equivalent background), ideally with ML work on chip-design data such as netlists, RTL or timing and power data

Practical experience adapting LLMs, whether through SFT, RLHF or comparable techniques

Command of Python and PyTorch, plus Hugging Face Transformers and similar tooling

Experience creating test harnesses for models and the data pipelines around them

Bonus: C++ and CUDA, GPU architecture, inference engines like vLLM or SGLang, distributed training, and exposure to Verilog or SystemVerilog

Self-directed and drawn to ambitious open-ended problems

On-site in the Silicon Valley area. No visa sponsorship or transfers.