Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The DCE Connectivity Hardware organization is one of Marvell's most strategically critical engineering groups, responsible for the full silicon lifecycle of the world's highest-performance electrical and optical connectivity products. The team designs and delivers advanced retimers, gearboxes, Active Electrical Cable (AEC) solutions, PCIe switches, Copper PHY, coherent-lite DSP, and Co-Packaged Optics technologies — products that sit at the physical layer of every major AI cluster, cloud data center, and carrier network on the planet.

The organization spans a globally distributed team of world-class engineers across North America, Europe, and Asia, working at the leading edge of CMOS process technology — from 5nm through 3nm FinFET and into 2nm GAAFET. With deep expertise across digital design, design verification, physical design, DFT, and silicon validation, the group operates with the rigor and velocity required to deliver first-silicon success on the industry's most complex, high-speed ASICs.

As AI-driven bandwidth demand continues to reshape the data infrastructure landscape, this team is defining what comes next — pushing the boundaries of 200G/lane SerDes, Co-Packaged Optics, and uLED integration to architect the connectivity fabric of the future.

What You Can Expect

Marvell is seeking a visionary Associate Vice President (AVP), Engineering to lead a critical engineering function within the DCE Connectivity Hardware organization. This role sits at the intersection of advanced CMOS digital design, high-speed SerDes, silicon validation, and multi-generational product execution — spanning 200G/lane PAM4 retimers and gearboxes, PCIe Gen7 and beyond, Active Electrical Cable (AEC) solutions, Copper PHY, coherent-lite DSP, and emerging Co-Packaged Optics and uLED technologies.

You are not simply managing an engineering team — you are shaping the execution engine that delivers industry-leading connectivity silicon from architecture through tape-out and into high-volume production on the world's most advanced process nodes, including 3nm FinFET and 2nm GAAFET. This role reports directly to the VP of Engineering, DCE Connectivity, and plays a central role in defining execution strategy, technology roadmap, and cross-site engineering delivery for products that set the pace of the industry.

What You Will Do

Engineering Leadership & Execution

Lead a globally distributed engineering organization spanning design, verification, physical design, DFT, and/or silicon validation across sites including Irvine, Santa Clara, Ottawa, Pavia, Aachen, Bucharest, Vietnam, and India

Own end-to-end execution of one or more major product families — from RTL design through tape-out, bringup, and production release

Drive first-silicon success across next-generation 200G/lane and beyond connectivity products on 3nm and 2nm process nodes

Establish and continuously improve design flows, verification methodologies, DFT strategies, and emulation infrastructure to accelerate delivery and quality

Technology Roadmap & Strategy

Partner with architecture, systems, and product management teams to define the technical roadmap for next-generation connectivity products

Provide engineering leadership on advanced process node transitions and emerging transistor architectures including GAAFET and backside power delivery

Champion AI-assisted design flows and automation to accelerate engineering productivity across the team

Evaluate and drive adoption of new EDA tools, methodologies, and automation frameworks

Cross-Functional & Customer Engagement

Collaborate closely with analog design, physical design, firmware, software, and product engineering teams to ensure seamless chip execution and customer readiness

Engage with key hyperscaler and carrier customers on technical requirements, product roadmaps, and engineering sample delivery

Represent the engineering organization in cross-BU forums, R&D management reviews, and executive-level program reviews

People & Organization

Build, develop, and retain a world-class engineering team; mentor senior engineers and directors toward technical and leadership excellence

Drive a culture of rigor, innovation, and accountability — consistent with Marvell's core behaviors

Lead FY performance and development goal-setting, talent reviews, and succession planning across the organization

What We're Looking For

15+ years of progressive engineering experience in semiconductor/ASIC design, with a proven track record of leading large-scale chip programs from concept to production

Deep technical expertise in one or more of: digital IC design (RTL/synthesis/STA), design verification and emulation, DFT, physical design, or silicon validation for high-speed connectivity products

Experience with advanced CMOS process nodes (7nm and below); familiarity with FinFET and GAAFET architectures is a strong plus

Demonstrated ability to lead globally distributed engineering teams of 50+ engineers across multiple time zones and cultures

Strong track record of delivering complex, multi-million-gate ASICs on aggressive schedules with first-silicon success

Experience with high-speed serial interfaces (PAM4, 200G/lane and beyond), optical DSP, PCIe, AEC, or Copper PHY is highly desirable

Excellent communication and executive presence; ability to influence across organizational boundaries and engage directly with customers and partners

BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field

Expected Base Pay Range (USD) 242,080 - 362,600, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.

Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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