At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

As an RTL Methodology Engineer , you will have a unique opportunity to work on AMD's next-generation CPU core and build the infrastructure, tooling, and AI-powered capabilities that multiply the efficiency and productivity of the entire Core RTL team. This is a high-leverage role: the flows you own are used by every RTL designer on the project, and you will be at the forefront of bringing modern AI and agentic tooling into the hardware design process. You will work in the center of an experienced, skilled, and motivated engineering team with a track record of success. As a member of the Core RTL team, you will work on the leading edge of processor technology and collaborate with Performance Modeling, Design Verification, Physical Design, and Post-Silicon teams to make AMD's ambitious future CPU roadmap a reality.

THE PERSON:

You approach challenges relentlessly with both critical thinking and creativity. You are energized by the idea of applying AI and automation to problems that have traditionally been solved by hand, and you have the judgment to know where it will pay off and where it won't. You work as part of a team with strong communication and collaboration skills. You have a solid understanding of modern CPU architecture and have ideas and/or the drive to make it even better. You are passionate about improving engineering tools and infrastructure and about continuous improvement. Does this describe you? If so, then join us!

KEY RESPONSIBILITIES:

p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item"> Execute and refine the methodology and tools needed to accomplish RTL design work

p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item"> Develop AI-powered tools and agentic workflows that accelerate RTL design, review, debug, and code quality — including LLM-based assistants, code generation and transformation, and automated analysis of design artifacts

p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item"> Own and advance the RTL static analysis ecosystem: linting flows, rule authoring and waiver management, SystemVerilog/Verilog parsers, ASTs, and custom code-analysis tooling

p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item"> Identify high-value opportunities to apply AI across the RTL design flow, prototype quickly, and drive successful prototypes into production use by the broader team

p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item"> Collaborate with a team of hardware and infrastructure engineers to develop best-in-class engineering infrastructure for RTL development

p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item"> Own, refine, and maintain critical tools that ensure successful, high-quality RTL development

p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item"> Team up with multi-disciplinary teams to find new ways to unlock efficiency in RTL development

p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item"> Contribute to silicon debug and product support as needed

PREFERRED EXPERIENCE:

Verilog/SystemVerilog RTL development within CPU, SoC, ASIC, or related digital-design environments

RTL linting, static analysis, design methodology, and code-quality tooling

HDL parsers, ASTs, or source-code analysis and transformation tools such as Verible, Slang, Verilator, Surelog, or comparable technologies

Building applications or engineering tools using large language models, including RAG, agentic frameworks, tool/function calling, prompt engineering, or related approaches

Applying AI coding assistants or agents within engineering-development workflows

Evaluating AI-tool quality and reliability through benchmarking, regression testing, or productivity measurement

Developing and owning internal engineering tools and automation

Strong proficiency with scripting languages such as Python, Perl, Ruby, Shell, and/or TCL

Programming experience with languages such as Python, Go, Java, C#, TypeScript, or comparable languages

Familiarity with digital-design workflows including synthesis, verification, physical design, place and route, and timing closure

Strong problem-solving and debugging skills

ACADEMIC CREDENTIALS:

BS, MS, or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field of study preferred.

This role is not eligible for visa sponsorship.

#LI-LC3

Benefits offered are described: AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.