A NauWork client is seeking a Principal Design Verification Engineer – CPU Core Hardware Prefetch to join their team. The position can be onsite, hybrid, or remote . Office locations for onsite/hybrid are Austin, TX, Santa Clara, CA, or Boston, MA.

This client is a well-funded semiconductor innovator building next-generation processor IP that powers everything from embedded devices to high-performance computing and AI infrastructure. They operate at the forefront of modern computer architecture, combining cutting-edge CPU design with a strong focus on scalability, configurability, and long-term ecosystem impact. Their teams include widely respected leaders in architecture and silicon design, and they are investing heavily in advanced verification methodologies to keep pace with rapidly growing complexity. For a senior verification expert, this is an opportunity to shape technology used across a broad range of markets while working in a highly collaborative, forward-looking environment.

In this role, the Principal Design Verification Engineer will own verification strategy and execution for CPU core hardware prefetch in a high-performance out-of-order core. This is a senior technical leadership position for someone who can define architecture-aware verification approaches, uncover and de-risk subtle microarchitectural issues early, and tackle the most challenging hardware prefetch verification problems. The engineer in this role will drive end-to-end verification, from block-level to core-level integration, and will be a key technical reference across the broader CPU DV organization. This is a chance to have direct impact on core microarchitecture quality while mentoring others and shaping reusable methodologies for future CPU generations.

Responsibilities:

Lead verification planning and execution for CPU hardware prefetch features in a high-performance out-of-order core, covering unit-level and core-level strategy, debug, coverage closure, and signoff readiness.

Define verification strategies, test plans, checkers, scoreboards, assertions, stimulus approaches, and coverage models for advanced hardware prefetch microarchitecture and its corner cases.

Drive verification of hardware prefetch behaviors including stream allocation and replacement, training from demand requests, prefetch generation, request replay and kill behavior, issue-queue interactions, and feedback-based control of prefetch aggressiveness.

Verify correctness of runtime configurability through hardware prefetch CSRs, including enablement, windowing, initial distance, maximum distance, growth thresholds, queue-allocation controls, and thresholds linked to L1/L2 cache and MSHR behavior.

Validate interactions between the hardware prefetch engine and the memory hierarchy, including DCache pipeline behavior, cacheable-read-only training conditions, MSHR fullness backpressure, L1/L2 prefetch targeting, and arbitration with other core-generated traffic.

Develop verification strategies for challenging corner cases such as stream misconfirmation/untraining, queue unavailability, threshold-based throttling, page-boundary behavior, multi-stream interactions, and correctness under diverse operating modes and software-programmed configurations.

Use architectural counters, self-checking tests, and microarchitectural observability to ensure prefetch behavior is functionally correct and robust under realistic, performance-sensitive traffic patterns.

Collaborate closely with architecture, RTL, performance, software, and verification teams from early feature-definition stages to review specifications, remove ambiguity, improve debuggability, and influence design from a verification perspective.

Apply appropriate verification methods—including simulation, formal techniques, emulation, and performance-oriented validation—to address high-risk or hard-to-observe hardware prefetch behaviors.

Lead efficient failure analysis and root-cause debug across specification, RTL, test content, assertions, and verification infrastructure.

Mentor engineers across the organization and help define reusable verification approaches, infrastructure, and methodologies for future CPU core generations.

Required Experience:

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

12+ years of relevant experience in CPU/core or SoC functional verification, with depth suitable for a Principal / T6-level role.

Deep understanding of computer architecture and modern CPU microarchitecture.

Strong object-oriented programming skills and experience developing complex verification infrastructure.

Direct experience with out-of-order CPU core verification.

Proven expertise in hardware prefetch verification or closely related CPU memory-subsystem verification, with the ability to translate architectural intent into effective verification strategies and execution plans.

Strong knowledge of verification methodologies, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.

Excellent debug skills and solid software/scripting fundamentals for building scalable DV infrastructure, automation, and analysis workflows.

Strong understanding of CPU memory behavior, including ordering-sensitive interactions, cache hierarchy effects, and how hardware prefetch interacts with demand traffic and overall system performance.

Preferred Experience:

Experience verifying advanced hardware prefetch architectures (e.g., stride-based or stream-based prefetchers with training, confirmation, throttling, and adaptive distance control).

Experience verifying prefetch engines integrated with DCache or memory-subsystem pipelines, including interactions with issue queues, MSHRs, cache feedback, and replay behavior.

Experience developing or reviewing verification content using performance counters, constrained-random traffic, directed corner-case scenarios, and software-driven stress patterns to validate prefetch correctness.

Experience with formal verification targeting bounded, control-intensive, or interface-sensitive microarchitectural problems.

Experience using emulation or other acceleration techniques to improve turnaround time on large CPU verification workloads.

Track record of effective collaboration with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.

Demonstrated technical leadership through mentoring, methodology influence, and cross-team execution on complex CPU verification programs.

To Learn More:

503-388-9585

833-NAU-WORK

careers.nauwork.com

Category: Engineering – Electrical (Semiconductor) Position: Principal Design Verification Engineer – CPU Core Hardware Prefetch Location: Hybrid – Austin, TX or Santa Clara, CA Job Type: Direct-Hire, Full-Time