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Synopsys has filed one layoff notice in the last twelve months, covering 128 workers, most recently August 2026. These are public filings with state labor departments, and an open role can sit alongside them. See the filings

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About the job

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years verifying silicon that cannot afford to fail in production, and you understand that catching the corner case at RTL saves months of pain downstream. The difference between a testbench that looks good in review and one that finds bugs is something you feel in your gut after running thousands of simulations and debugging failures that made no sense until they suddenly did.

You think in coverage holes, not checklist completion. When someone says, 'we hit 100% code coverage,' you are the engineer asking what scenarios were never exercised and why the assertions did not catch that protocol violation three weeks ago. Mentoring matters to you because you remember being the engineer staring at a waveform at 9 PM trying to understand why a transaction dropped. You do not need perfect specs to get started. You read the RTL, ask the design team the right questions, and build a test plan that reflects how the block will break.

What You'll Be Doing

Define and track verification test plans for DDR PHY and memory subsystem IP blocks, translating architecture specs into executable verification strategies

Design and write constrained-random System Verilog testbenches using UVM, building reusable verification components that scale across product families

Write System Verilog assertions and functional coverage models to close coverage gaps and catch protocol violations

Debug RTL and gate-level simulation failures, working with design engineers to root-cause issues in complex memory interface logic

Perform code coverage analysis and drive coverage closure, identifying untested paths and corner cases that matter

Mentor verification engineers earlier in their careers, reviewing test benches, debugging strategies, and verification plans

Integrate AI-assisted verification tools and workflows into the team's methodology

The Impact You Will Have

Your test plans and coverage models will directly determine whether critical bugs are caught before tape out or discovered in silicon

The UVM environments you build will be reused across multiple product generations, shaping how the team verifies memory IP for years

Your debugging work will uncover RTL issues that would have caused customer re-spins, saving months of schedule and millions in mask costs

The assertions and coverage you write will become the safety net that catches regressions as the design evolves

Your mentorship will accelerate how quickly new engineers become productive contributors

The verification strategies you define will influence how Synopsys memory IP is validated across the product portfolio

What You'll Need

Bachelor’s degree in electrical engineering or computer engineering with 8+ years of hands-on ASIC verification experience

Deep proficiency in UVM methodology and System Verilog, you have built test benches that found bugs

Understanding of DDR memory architecture and DDR PHY design, including timing, training, and calibration flows

Knowledge of DFI protocol, memory controllers, or memory subsystem integration, preferred

Solid scripting ability in Perl or Python for automation, result parsing, and flow development

Proven debugging skills across RTL and gate-level simulations

Experience with AI-assisted verification tools and workflows is a plus

Who You Are

You can look at a failing test, a 10,000-line waveform, and a vague bug description and figure out what actually went wrong

You push back when a test plan is too shallow or a coverage model misses the scenarios that will actually break in the field

You write assertions that catch real bugs, not ones that just make the coverage report look better

You can explain a complex verification failure to a design engineer in a way that gets them to the right line of RTL

You are comfortable being the senior technical voice in a room, whether that is a test plan review or a tape out readiness discussion

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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