Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers. Our portfolio of technology helps power our world ---come join our team and see how YOU can make a difference.

Job Description:

he candidate will be part of the memory design team supporting the definition, specification, system simulation and implementation of future DDR, LPDDR related product IPs. The focus of the activity will be centered around the circuit architecture and design of critical high-speed analog and digital blocks, definition of specifications for the high speed data path.

Location: San Jose-US

Responsibilities:

Ownership of high speed analog/mixed signal designs at chip and block level

Design, simulate and characterize high-performance and high-speed circuits

Create high level model for design tradeoff analysis and behavior model for verification simulations

Work with digital/system teams to define architecture and design plan to achieve budget, schedule and project deliverable goal

Create floor plan and work with layout team to demonstrate post extraction performance

Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow

Work with the lab and system team for test plan, silicon bring-up and characterization

Understand and disseminate applicable standards and its relevance in a given project to team

Mentor junior designers

Participate and contribute to the definition of development flows that improve efficiency and quality of design execution

Qualifications:

MS EE and 7+ years or PhD EE and 5+ years’ experience of analog/mixed-signal circuit design

Prior experience in high speed analog circuits like Transmitter, Receiver, PLL, DLL, PI or clock distribution

Solid knowledge of design principles for practical design tradeoffs

Solid knowledge of the basic building blocks like bias, op-amp and LDO

Experience in designing memory interfaces such as DDR 4/5 or serial links such as PCIE is highly desirable

Experience in modeling with Verilog-A, Verilog, matlab is desirable

Experience in working in leading R&D and future technology development projects is desirable

Monolithic Power Systems, Inc. (MPS) is an Equal Opportunity Employer and embraces diversity in our employee population. It is the policy of MPS to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status or special disabled veteran, marital status, pregnancy, genetic information, or any other legally protected status.