EDA and CAD Lead Engineer / Manager
Attotude
Menlo Park, CA · Posted October 28, 2026
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Where Menlo Park, CA ranks
Where Menlo Park, CA placed in our monthly rankings, month by month. Each month stays online at its own address.
November 2026
- #5Best cities for AI-skill jobs in the West Coast32% · of 71
- #6Best cities for financial services pay after cost of living$164k · of 33
- #6Best cities for AI-skill jobs32% · of 100
- #7Best cities for entry-level jobs that want AI skills in the West Coast21% · of 54
- #11Best all-round cities for AI careers in the West Coast75 / 100 · of 39
- #12Best cities for pay after cost of living in California$169k · of 32
Rankings about engineering jobs
- Best cities for software and engineering jobs #1 San Francisco (3,412 openings)
- Best cities for engineering pay after cost of living #1 San Mateo ($216k)
- Most requested AI skills in engineering jobs #1 AI tools in daily work (6.1%)
- AI tools named most often in engineering jobs #1 Claude (1.7%)
- Employers with the most engineering jobs #1 Amazon (2,992 roles)
How AI is used in this kind of work
AI use among electronics engineers, except computer is little observed so far. Measured exposure for electronics engineers, except computer: 10% (little observed).
Share of this job’s tasks that AI is already used for at work, from real usage. It is not a forecast of job loss, and a low number means no use seen yet. Source: Anthropic Economic Index.
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About the job
We are seeking an experienced EDA/CAD lead engineer to join our growing team. In this role, you will be part of the experience design and layout team to develop cutting-edge mixed-signal ICs. You will be involved in the technical aspects of the ASIC design and development, from concept through to production. This is a hands-on technical position that requires in-depth technical expertise, and the ability to work in a team of highly experienced engineers to accomplish the goals.
Key Responsibilities:
Floor planning, IP integration
Pad Ring creation
Work with analog/mixed-signal designers for high-performance layout integration
Work with digital designers for DFT/ATPG/Scan logic integration
Perform LVS/DRC checks and fix issues
Integration of Digital/RF/mmWave blocks into IC Top Level
Collaborate with cross-functional teams to ensure timely project execution and design tape-outs
Stay updated with the latest trends and technologies in wideband high speed IC design and apply them to improve project outcomes
Occasional travel to the Bay Area (
Qualifications:
5+ years of hands-on experience in CMOS (bulk and advanced FinFET) IC implementation in multiple process technologies
Strong experience with Cadence (and various EDA) tools is required (Virtuoso, Calibre, Voltus)
Experience in multiple dedicated tapeout support is required
Scripting language experience in Tcl, Python, Perl, Makefile, and shell scripts are required
Education:
Formal Cadence digital layout training or certification is required
Bachelor’s degree in electrical engineering, computer science or a related field is preferred
Preferred Skills:
Experience with CMOS, and/or SiGe Process Development Kits
Experience working on a multidisciplinary team with RF/Mixed Signal, Hardware, Firmware, and Software engineers
Strong communication and teamwork skills
Experience working in fast-paced environments with a strong track record of delivering high-quality designs on time.
Benefits :
Competitive salary
Stock options plan
Paid time off
Health benefits