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Systemverilog

About the job

A NauWork client is seeking a Design Verification Engineer to join their team. The position is onsite in Palo Alto, CA .

This client is an early stage startup focused on AI research and modern chip design. Their team is building AI models and systems that help explore, generate, optimize, and verify new hardware aiming to dramatically reduce ASIC design time, cost, and manual effort. The organization is venture-backed and built by experienced researchers and engineers from leading technology companies and top academic environments. They operate with an early-stage, high-ownership mindset and are pushing toward real-world silicon outcomes that impact high-volume production.

In this role, the Design Verification Engineer will be a key contributor in verifying AI-assisted and AI-generated ASIC designs headed toward tape-out on advanced process nodes. This position sits at the intersection of rigorous, proven DV practices and emerging AI-driven design automation, offering the opportunity to influence how verification is done as these workflows evolve. The ideal candidate has end-to-end verification experience across block and SoC levels, and is comfortable moving quickly across multiple fast-paced programs. Candidates who have verified AI accelerators, NPUs, or inference-focused ASICs will be especially well-aligned.

Responsibilities:

Own functional verification for AI-generated and AI-assisted ASIC designs from block/IP level through full SoC integration

Build and execute UVM-based verification environments, including testbenches, checkers, and coverage models

Develop verification plans and test strategies for internal development and customer chip programs

Partner with architecture, design, and AI/ML stakeholders to produce simulation- and emulation-ready verification collateral

Provide DV best practices and domain expertise to help encode robust verification methods into AI-driven verification flows and tooling

Deliver results against aggressive tape-out schedules while balancing quality, coverage, and execution speed

Required Experience:

10–15 years of design verification experience in ASIC/SoC development

Strong hands-on expertise with SystemVerilog and UVM verification methodology

Demonstrated experience verifying complex SoCs end-to-end

Experience creating verification plans, coverage models, and microarchitectural/functional checkers

Ability to collaborate cross-functionally with design, architecture, and software/ML teams

Background verifying AI accelerators, NPUs, or inference ASICs (highly preferred)

Comfort operating in a fast-moving startup or highly execution-focused environment

To Learn More:

503-388-9585

833-NAU-WORK

careers.nauwork.com

Category: Engineering - Electrical (Semiconductor)

Position: Design Verification Engineer

Location: Fully Remote

Job Type: Direct-Hire, Full-Time