A NauWork client is seeking a Formal Verification Architect to join their team. The position is hybrid or fully remote , with options in San Francisco Bay Area, CA; Portland, OR; Austin, TX; or Remote (US).

This well-capitalized semiconductor innovator builds highly configurable processor IP used by customers designing custom silicon across data center, AI infrastructure, and high-performance computing , as well as embedded and automotive markets. Their technology is rooted in an open instruction-set ecosystem and is designed to scale from low-power devices to high-performance, out-of-order compute platforms . What sets them apart is a generator-driven approach: instead of delivering a single fixed core, they deliver parameterized designs that can produce many optimized implementations. As the portfolio grows in performance, scale, and configurability , they are investing heavily in next-generation verification methodology to keep quality and correctness ahead of complexity.

In this architect-level role, the Formal Verification Architect will define and drive overall verification strategy (with a strong emphasis on formal) across a broad CPU IP portfolio. This position is built for someone who wants to influence architecture and RTL decisions, not simply verify what already exists, by shaping designs to be more provable and more robust. The work extends beyond verifying one configuration to proving correctness across entire families of generated designs, requiring deep expertise in abstraction, compositional proof techniques, and proof convergence. The impact is company-wide: the methodologies, test strategies, and verification content defined here will raise confidence across multiple product lines and generations.

Responsibilities

Define the overall verification strategy (including formal, simulation, and test planning) for a portfolio of configurable CPU IP, with emphasis on high-performance and infrastructure-class designs

Architect end-to-end verification flows from property/specification definition through proof closure and test execution across IP subsystems, full CPU pipelines, and multi-core/SoC configurations

Identify high-risk architectural corner cases (e.g., microarchitectural hazards, pipeline interlocks, cache coherence edge cases, memory ordering, exception/interrupt behavior, privilege transitions, security boundaries) and create targeted strategies for exhaustive coverage

Build and maintain reusable, generator-aligned verification methodologies so properties, models, and test content apply across a broad configuration space (not rewritten per instance)

Create abstraction hierarchies and scalable proof strategies (e.g., cut-point abstraction, assume/guarantee decomposition, compositional approaches, over-approximation) to manage complexity while preserving rigor

Develop parametric specifications and formal models that hold across legal instantiations and generator parameters (cache sizes, pipeline depth, XLEN, ISA extensions, privilege levels, etc.)

Partner with design and architecture teams to recommend structural or microarchitectural changes that improve formal tractability and overall correctness

Drive “correct-by-construction” approaches by encoding invariants into generator/design structure to prevent entire bug classes

Define formal closure metrics and quality standards (proof depth, witness quality, vacuity checks, coverage expectations)

Develop and refine proof convergence strategies for complex, high-performance (including out-of-order) designs

Lead evaluation/selection and rollout of formal tools and infrastructure across programs

Introduce advanced techniques where useful (equivalence checking, security-property verification, fault injection analysis)

Coordinate with software/firmware and compliance stakeholders to align verification scope with architecture and compliance requirements

Represent verification methodology externally as needed (customer technical support, EDA partnerships, industry engagement)

Required Experience

10+ years in formal verification and hardware verification, with substantial experience on complex CPU/SoC/processor IP programs

Proven track record defining and owning verification strategy (not just executing within an existing plan)

Strong expertise with formal verification tools (e.g., JasperGold, VC Formal, Questa Formal, or comparable platforms)

Strong SystemVerilog and SVA skills, including parameterized assertions and temporal property development

Strong knowledge of high-performance CPU microarchitecture , including out-of-order execution, superscalar pipelines, branch prediction, load-store units, memory ordering, floating point, SIMD/vector processing, and cache hierarchy

Experience formally verifying cache coherence protocols and memory subsystems using formal methods

Demonstrated ability to scale formal using abstraction/decomposition techniques

Familiarity with HDLs (SystemVerilog/Verilog/VHDL); exposure to generator-based flows (e.g., Chisel/FIRRTL) is a plus

Experience with proof convergence methods (k-induction, invariant strengthening, coverage analysis, etc.)

B.S., M.S., or Ph.D. in EE, CE, CS, or a related field

To Learn More:

503-388-9585

833-NAU-WORK

careers.nauwork.com

Category: Engineering - Electrical (Semiconductor)

Position: Formal Verification Architect

Location: Hybrid (San Francisco Bay Area, CA / Portland, OR / Austin, TX) or Fully Remote (US)

Job Type: Direct-Hire, Full-Time