A NauWork client is seeking a Principal Design Verification Engineer – CPU Core Frontend to join their team. The position can be onsite, hybrid, or remote. Office locations for onsite/hybrid are Austin, TX, Santa Clara, CA, or Boston, MA.

This NauWork client is a well-funded semiconductor innovator building next-generation processor technology used from embedded systems all the way up to data center and AI infrastructure. Operating at the intersection of advanced computer architecture and system-level design, they emphasize flexibility, scalability, and long-term ecosystem impact. The team includes recognized leaders in CPU architecture and silicon design, and the company is investing heavily in state-of-the-art verification methodologies to keep pace with rapidly increasing design complexity. This is a chance to join a high-visibility organization that is helping shape the future of compute platforms across multiple markets.

In this role, the Principal Design Verification Engineer will own the verification strategy and execution for the CPU core frontend of a high-performance out-of-order core. This is a senior technical leadership position, ideal for someone who thrives on defining architecture-aware verification approaches, identifying microarchitectural risk early, and tackling the most challenging frontend verification problems. The engineer in this role will collaborate closely with architecture, RTL, performance, and broader DV teams to ensure design intent is captured correctly and that verification signoff is robust and scalable. Beyond day-to-day execution, this person will help shape reusable methodologies and infrastructure that influence multiple CPU core generations.

Responsibilities:

Lead verification planning and execution for CPU frontend functionality in a high-performance out-of-order core, with ownership spanning branch prediction and instruction fetch behavior.

Define verification strategy, test plans, checkers, scoreboards, assertions, stimulus strategies, and coverage models for frontend microarchitecture and associated corner cases.

Drive verification of branch prediction structures and flows, including direction prediction, indirect target prediction, return prediction, predictor update/training behavior, redirect generation, recovery, and interaction with global history or related predictor state.

Drive verification of instruction fetch behavior, including fetch packet correctness, PC sequencing, fetch ordering, ITLB/translation interactions, exception reporting, cache-related fetch behavior, and redirect handling after misprediction or flush conditions.

Partner with architects and designers from early feature-definition stages to review specifications, resolve ambiguity, and enhance frontend debuggability and verification completeness.

Own block-level and core-level verification closure for frontend features, including coverage analysis, gap identification, bug triage, and signoff readiness.

Apply the appropriate verification method for each challenge, including simulation, formal techniques, and emulation for high-risk or hard-to-observe frontend behaviors.

Mentor engineers across the organization and drive reusable verification approaches, infrastructure, and methodologies for future CPU core generations.

Required Experience:

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

12+ years of relevant experience in CPU/core or SoC functional verification, including substantial exposure to high-performance CPU verification at a Principal/T6 level.

Direct experience with out-of-order CPU core verification and a strong understanding of CPU microarchitecture.

Deep understanding of computer architecture.

Proven experience as a seasoned developer using object-oriented programming principles.

Deep expertise in CPU frontend verification, especially branch prediction and instruction fetch verification.

Strong knowledge of verification methodologies, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.

Excellent debug skills and the ability to translate architectural intent into an effective verification strategy and execution plan.

Strong software and scripting fundamentals for building scalable DV infrastructure, automation, and analysis workflows.

Preferred Experience:

Verification experience with advanced frontend architectures or decoupled fetch/prediction pipelines in high-performance CPU cores.

Hands-on experience with branch prediction microarchitecture such as BTB-style structures, target prediction, return prediction, global-history-based predictors, predictor training, and misprediction recovery.

Experience using formal verification to address bounded, control-heavy, or interface-sensitive frontend problems.

Experience using emulation or other acceleration techniques to improve turnaround times on large CPU verification workloads.

Experience collaborating across architecture, performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.

Demonstrated technical leadership through mentoring, methodology development, and cross-team execution on complex CPU verification efforts.

What Success Looks Like:

Frontend verification plans comprehensively capture real architectural and microarchitectural risks early in the design cycle.

Challenging branch prediction, fetch, redirect, and recovery bugs are found early, debugged efficiently, and resolved with durable solutions.

Verification quality improves across the broader CPU DV organization through stronger methodology, reusable infrastructure, and clear technical leadership.

Architecture, design, and DV teams rely on this engineer to solve the most complex frontend verification challenges in high-performance CPU development.

To Learn More:

503-388-9585

833-NAU-WORK

careers.nauwork.com

Category: Engineering – Electrical (Semiconductor)

Position: Principal Design Verification Engineer – CPU Core Frontend

Location: Local/Hybrid – Austin, TX or Santa Clara, CA

Job Type: Direct-Hire, Full-Time