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About the job

A NauWork client is seeking a Senior/Prinicial IC Packaging Engineer to join their team. The position is on-site in greater San Jose, CA .

This venture-backed semiconductor innovator, headquartered in the greater San Jose is redefining how data moves inside next-generation computing systems. Founded by seasoned leaders from the optical networking space and backed by top-tier VCs, the company focuses on ultra-low power, high-density optical interconnects for AI data centers, high-performance computing, and advanced semiconductor applications. Their microLED-based approach is solving interconnect bottlenecks that limit today’s AI and cloud infrastructures, enabling performance and efficiency levels that traditional electrical and laser-based solutions struggle to reach.

In this Senior IC Packaging Engineer role, the successful candidate will own and drive advanced packaging process development from early concept through high-volume manufacturing. This position focuses heavily on 2.5D/3D integration, TSV reveal, and wafer-level bumping for high-performance optical engine and semiconductor applications. The engineer will collaborate closely with OSAT partners, internal integration and design teams, and reliability/test functions to bring new packaging technologies to robust yield at wafer scale. This is a high-impact, hands-on role ideal for someone who thrives on solving complex process challenges and wants to help define the roadmap for next-generation packaging solutions.

Responsibilities:

Lead the architecture, design, and development of advanced semiconductor packaging solutions, including 2.5D/3D IC, System-in-Package (SiP), Flip Chip, and Wafer-Level Packaging.

Drive development, characterization, and optimization of TSV (Through-Silicon Via) reveal processes, including back grind, CMP, dielectric/barrier reveal etch, and thickness/uniformity control across wafer thinning stacks.

Own C4 bumping process flows (UBM deposition, solder bump plating or ball drop, reflow, and flux clean) for flip-chip and 3D-IC applications.

Develop and maintain process control plans (SPC), DOEs, and yield improvement roadmaps for optical engine packaging and bumping modules.

Partner with integration engineering to co-optimize TSV reveal with downstream processes such as hybrid bonding, micro-bump, or RDL.

Troubleshoot process excursions using FA data, cross-sections, and metrology (e.g., CD-EM, profilometry, XRF, AOI) to identify and resolve issues such as TSV protrusion variation, via reveal non-uniformity, bump voiding, or co-planarity problems.

Support new product and technology introduction (NPI) from early pathfinding through transfer to high-volume manufacturing.

Collaborate cross-functionally with design, reliability, and test teams to ensure package-level electrical and mechanical performance targets are met.

Mentor junior engineers and contribute to internal process documentation, best practice standards, and knowledge sharing.

Required Experience:

MS or PhD in Materials Science, Electrical Engineering, Chemical Engineering, Mechanical Engineering, or a related field.

5+ years of hands-on experience in semiconductor packaging or wafer fab process engineering, including work with major OSATs (e.g., ASE, Amkor, SPIL or similar). A strong personal network within key OSATs is highly advantageous.

Direct, hands-on experience with TSV reveal processes (grinding, CMP, dielectric reveal, thickness metrology) and C4 bumping (UBM, electroplating or solder ball attach, reflow).

Strong understanding of 2.5D/3D packaging architectures (e.g., interposers, chiplets, HBM integration; hybrid bonding experience is a plus).

Deep understanding of semiconductor device physics, packaging materials, and thermal/mechanical analysis.

Experience with statistical process control, DOE methodologies, and yield analysis.

Familiarity with metrology and inspection tools relevant to bumping/TSV (e.g., CD-SEM, AFM, profilometers, X-ray, AOI/SEM defect review).

Working knowledge of cleanroom fab operations and contamination control.

Excellent cross-functional communication skills and comfort working with equipment OEMs and multi-site teams.

Nice to Have:

Experience with copper pillar bumping, micro-bump, or hybrid bonding processes.

Background in wafer thinning and temporary bonding/debonding for advanced node packaging.

Exposure to reliability testing for packaged parts (e.g., thermal cycling, electromigration, HAST).

Experience supporting high-volume manufacturing ramp in an OSAT or IDM environment.

To Learn More:

503-388-9585

833-NAU-WORK

careers.nauwork.com

Category: Engineering – Electrical (Semiconductor)

Position: Senior/Principal IC Packaging Engineer

Location: San Jose Area, CA (On-site)

Job Type: Direct-Hire, Full-Time