Principal DV Engineer - CPU Core

A NauWork client is building a bench for their high-performance, out-of-order RISC-V CPU core targeting data center and AI infrastructure workloads. They are conducting a coordinated hiring process for three Principal Design Verification Engineers – CPU Core . Each owns a different piece of the CPU core, working side-by-side within one CPU Core DV organization. The positions can be onsite, hybrid, or remote . Onsite locations are Austin, TX, Santa Clara, CA, and Boston, MA.

This NauWork client is a well-funded semiconductor innovator building next generation processor technology that powers everything from embedded systems to high-performance data center and AI infrastructure. They operate at the intersection of cutting-edge microarchitecture and rigorous system-level engineering, with a mission to deliver highly flexible, scalable compute platforms. Backed by significant investment and led by industry-recognized experts in CPU design and verification, they offer the opportunity to work on technically ambitious programs that shape the future of custom silicon. Engineers here have a real voice in architecture, methodology, and long-term roadmap decisions.

The Principal Design Verification Engineers will join a CPU Core DV organization focused on a new high-performance, out-of-order RISC-V core targeting data center and AI-class workloads. The three Principal-level openings are Frontend, LSU, and Hardware Prefetch. This is a top-tier individual contributor track: the people in these roles will be the go-to expert for the most complex verification challenges in their domain, driving methodology, mentoring others, and owning end-to-end signoff. It’s an ideal environment for someone who wants scope, technical depth, and impact without formal people management.

Responsibilities:

Own end-to-end verification of a core microarchitectural unit or subsystem—from test planning and architecture through execution, closure, and signoff—for a next-generation, high-performance out-of-order CPU core.

Develop, maintain, and evolve UVM-based testbenches, including constrained-random stimulus, functional coverage models, assertions, scoreboards, and checkers.

Apply formal verification tools and techniques to close hard-to-hit corner cases and prove properties that are impractical to cover solely via simulation.

Leverage emulation for high-throughput, long-sequence, and system-level scenarios where traditional simulation is insufficient.

Debug complex RTL issues across interfaces and neighboring blocks, driving root-cause analysis in close collaboration with design and architecture teams.

Mentor other DV engineers, review test plans and testbench code, and contribute to reusable verification methodology and best practices across the CPU Core DV group.

Uphold verification signoff standards appropriate for data center and AI infrastructure-grade compute, where resiliency, correctness, and scalability are paramount.

Required Experience:

12+ years of functional verification experience on CPU or complex SoC programs.

Deep, hands-on expertise with SystemVerilog and UVM, including constrained-random and coverage-driven verification methodologies.

Proven experience applying formal verification at the CPU/core or comparable complexity level.

Experience with emulation-based verification for high-performance or system-level validation.

Strong software engineering fundamentals, including object-oriented programming skills and fluency in Python for verification automation and infrastructure.

Demonstrated track record of owning verification for a complex unit or subsystem end-to-end—from planning through closure and signoff—on prior CPU or SoC programs.

Evidence of technical mentorship and leadership: reviewing others’ work, elevating methodology, and serving as a key resource for the most challenging debug issues.

BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.

Preferred Qualifications:

Prior verification experience on out-of-order CPU cores (e.g., RISC-V, Arm, x86, MIPS, or similar architectures).

Background verifying data center or AI infrastructure-class compute, where scale, availability, and resiliency are first-class requirements.

History of building or significantly extending reusable DV infrastructure adopted across multiple projects or teams.

Contributions to verification methodology standards or internal best-practice frameworks.

Experience partnering closely with RTL design and performance/architecture teams to jointly resolve correctness and performance-sensitive issues.

Focus Areas – Role Alignment

All openings share the same core responsibilities and requirements with variable block focus areas.

CPU Core Frontend (Branch Prediction & Instruction Fetch)

– Speculative, control-flow-heavy front-end including branch prediction, instruction fetch, misprediction recovery, and instruction-side translation interactions.

CPU Core LSU (Load-Store Unit / Memory Ordering & Coherency)

– Memory ordering, consistency and weak-ordering models, atomics, cache coherency, overlapping accesses, and formal-heavy memory-model verification.

CPU Core Hardware Prefetch

– Hardware prefetch engines with both correctness and performance focus, including stream/stride detection, cache/MSHR interactions, runtime configurability, and performance-sensitive traffic pattern validation.

To Learn More:

503-388-9585

833-NAU-WORK

careers.nauwork.com

Category: Engineering – Electrical (Semiconductor)

Position: Principal Design Verification Engineer – CPU Core

Location: Hybrid – Austin, TX or Santa Clara, CA

Job Type: Direct-Hire, Full-Time