Principal DV Engineer - CPU Core High Performance

A NauWork client is seeking a Principal Design Verification Engineer – High Performance CPU Core to join their team. The position is remote or can be based in Austin, Texas, or Santa Clara, California .

This semiconductor company is advancing processor technology for demanding, data-intensive applications. Their work supports innovation across artificial intelligence, machine learning, automotive, data center, mobile, and consumer markets. Collaborative engineering teams tackle complex computing challenges with an emphasis on scalable technology and rigorous verification. Engineers have the opportunity to help shape the next generation of high-performance computing.

This Principal individual-contributor role offers ownership of verification strategy for high-performance CPU core units. The engineer will tackle challenging microarchitectural problems across areas such as Frontend, Midcore, Load-Store Unit, and Hardware Prefetch. Working closely with architecture, RTL, performance, and verification teams, they will identify risks early and help deliver signoff-quality designs. The position offers an opportunity to influence reusable methodology and raise verification quality across future core generations.

Responsibilities:

Own verification planning and execution for one or more high-performance out-of-order CPU core areas, with typical scope across Frontend, Midcore, Load-Store Unit, Hardware Prefetch, or related core-level interactions.

Drive block-level and core-level verification planning, debug, coverage analysis, and closure for complex CPU features and microarchitectural behavior.

Define verification strategies for challenging behaviors such as instruction fetch, branch prediction, issue and dispatch behavior, pipeline interactions, load/store ordering, hazard handling, memory consistency, and hardware prefetch correctness.

Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.

Partner closely with architecture and design teams from early feature-definition stages to review specifications, identify ambiguity, and improve design debuggability and verification quality.

Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.

Contribute reusable methodology, infrastructure, and technical guidance that improves productivity and verification quality across future core generations.

Verification plans capture the real architectural and microarchitectural risks early and completely.

Difficult CPU bugs are found early, debugged efficiently, and closed with durable solutions.

Coverage quality and testbench quality improve meaningfully under their ownership.

Architecture, design, and DV teams rely on them as a strong technical partner for difficult high-performance CPU verification challenges.

Required Experience:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

7+ years of relevant experience in ASIC, CPU/core, or SoC design verification.

Strong hands-on experience with SystemVerilog and UVM-based verification.

Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.

Experience in one or more high-performance CPU areas such as Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.

Strong knowledge of verification flow methodology, including test planning, constrained-random or directed stimulus generation, failure analysis, coverage analysis, and coverage closure.

Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.

Experienced developer using Object-Oriented Programming principles.

Preferred Experience:

Experience with out-of-order core verification.

Experience using formal verification and/or emulation for high-risk or performance-sensitive verification problems.

Experience collaborating with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.

Experience mentoring engineers and influencing verification methodology beyond the immediate block or feature area.

Familiarity with Python, C/C++, or other scripting/programming languages used for DV infrastructure and automation.

Deep understanding of computer architecture is desired.

To Learn More:

503-388-9585

833-NAU-WORK

careers.nauwork.com

Category: Engineering - Electrical (Semiconductor) Position: Principal Design Verification Engineer – High Performance CPU Core Location: Remote or Austin, Texas, or Santa Clara, California Job Type: Direct-Hire, Full-Time