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About the job

A NauWork client is seeking a Senior/Principal Interconnect Design Engineer to join their team. The position can be fully-remote or hybrid/on-site (multiple locations) .

This is with a well-capitalized semiconductor innovator building next-generation processor and system IP used in custom silicon across markets like and making a strong push into innovating within the AI infrastructure/data center space. Their engineering culture blends rigorous hardware design with software-style iteration speed, focusing on scalability, configurability, and long-term ecosystem impact. The team includes respected leaders in computer architecture and silicon design, with opportunities to influence widely deployed platforms.

This role involves the “uncore plumbing” that enables high-performance, multi-core SoCs - designing TileLink interconnects, cache controllers, coherence infrastructure, and protocol bridges. Rather than writing one-off RTL blocks, you’ll build configurable RTL generators, enabling reusable IP that can self-configure across many system topologies. The work is highly technical and impactful, spanning architecture, implementation, performance tuning, and close collaboration with design verification. It’s an excellent fit for engineers who like designing systems from the ground up and who think about hardware the way strong software engineers think about code.

Responsibilities:

Architect, design, and implement TileLink interconnects, cache controllers, protocol bridges, and related infrastructure as configurable RTL generators

Build generator-based IP that can self-configure to connect optimally across complex multi-core and multi-system designs, reducing manual integration/wiring effort

Drive performance and efficiency improvements for cache coherence in multi-core and multi-system configurations

Integrate new IP, including contributions that support auto-generated documentation, verification collateral, and packaged software

Partner with design verification to define verification strategies and execute thorough test plans

Produce and maintain clear technical documentation to support cross-team development

Required Experience:

Strong knowledge of cache architectures and cache coherency

Experience with NoCs and/or other interconnect fabrics

Fluency with common bus protocols (e.g., AXI, AHB, APB, CHI), including the ability to architect protocol bridges

Strong software engineering fundamentals (object-oriented and functional programming, metaprogramming/templates, compiler/DSL concepts, test-driven development)

Proficiency with RTL design using Verilog, SystemVerilog, and/or VHDL

BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience

To Learn More:

503-388-9585

833-NAU-WORK

careers.nauwork.com

Category: Engineering - Electrical (Semiconductor)

Position: Staff Interconnect Design Engineer

Location: Hybrid/On-site (US-based) - update accordingly

Job Type: Direct-Hire, Full-Time