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About the job

A NauWork client is seeking a CPU Power Management Design Engineer to join their team. The position can be fully-remote, on-site or hybrid (US - multiple locations) .

This well-capitalized semiconductor organization develops next-generation processor IP used across multiple domains, and is making a strong push into the high performance data-center/AI infrastructure domain. Their team includes respected leaders in computer architecture and silicon design, and they’re known for delivering real silicon on tight iteration cycles. Candidates who enjoy building foundational CPU/SoC technology where design choices directly impact performance, thermals, and battery life will find strong technical ownership and visibility here. The environment emphasizes collaboration across architecture, verification, physical design, and software to ship production-quality IP.

In this role, the engineer will own the “control plane” that keeps CPU/SoC silicon stable, efficient, and responsive across power states. They’ll translate architecture requirements into micro-architecture specifications and implement robust solutions for power sequencing, retention, resets, and complex clocking strategies. The work spans the full lifecycle from early definition through tapeout, with close partnership across DV, physical implementation, and software enablement. It’s a hands-on opportunity to solve one of the most consequential challenges in modern CPU design: delivering high performance without sacrificing energy efficiency and reliability.

Responsibilities:

Partner with CPU/SoC architects to define power-management requirements and operating modes

Architect, design, and implement clock, reset, and power-management logic (e.g., PMU design, power state machines, sequencing)

Develop and maintain micro-architecture specifications as designs evolve

Drive power-aware simulation and collaborate with DV on verification strategy and test plans

Work with physical implementation teams to achieve frequency, area, and power targets

Collaborate with software teams to enable, validate, and optimize power-management features at the system level

Required Experience:

Experience designing CPU/SoC clocking, reset, and power-management logic

Demonstrated skillset in key areas such as:

Reset architecture, control, and robust reset strategies

Clock distribution, dynamic clocking, clock gating, and CDC considerations

Power state modeling/definition, PMU implementation, retention logic, and power-up/down sequencing

DVFS and di/dt mitigation techniques

DFT/MBIST integration considerations, debug hooks, and error handling in CPU environments

Power-aware simulation methods

RTL development skills in Verilog or SystemVerilog

Working knowledge of RTL quality/signoff checks (Lint, CDC, RDC)

Track record of contributing to CPU/SoC programs from architecture definition through tapeout

BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience

To Learn More:

503-388-9585

833-NAU-WORK

careers.nauwork.com

Category: Engineering - Electrical (Semiconductor)

Position: CPU Power Management Design Engineer

Location: Fully-Remote or On-site/Hybrid (US)

Job Type: Direct-Hire, Full-Time